"The rich feature set and easy-to-use graphical user interface of CoreConsole greatly eases implementation of Actel's CoreMP7 soft IP microprocessor in our FPGAs," said Yankin Tanurhan, senior director, applications and IP solutions at Actel. "The development of this tool demonstrates Actel's commitment to advancing the use of the industry-leading ARM7 family technology within programmable logic devices and making FPGA-based system development obtainable for every designer."

A Robust Subsystem Builder

Use of Actel's CoreMP7 for system-level designs requires the implementation of a supporting subsystem around the microprocessor core. Implementation of this subsystem, which includes interrupt controllers, memory controllers, timers, serial interfaces, I/O ports and Power-on Reset (POR) circuitry, can be a tedious and time-consuming process if done manually. CoreConsole facilitates the implementation and configuration of the subsystem by automating the stitching of the components and allowing users to assemble the subsystem graphically at the function level, thus cutting development time from days to minutes.

An Effective IP Delivery System and Block Stitcher

Operating at the design-entry phase of the development process, CoreConsole is a bus-centric tool that automatically connects IP cores to the interconnect bus. The tool includes a block stitcher that enables IP blocks, including user IP, to be easily stitched together into synthesizable and simulatable RTL that is usable in Actel's Libero Integrated Design Environment (IDE). Additionally, CoreConsole contains an IP Vault that provides access to Actel's CoreMP7, the subsystem components and other IP that can be licensed from Actel's DirectCore portfolio, as well as third-party IP from Actel's CompanionCore partners.

CoreConsole is implemented at a level of abstraction above the RTL and is independent of the interconnect bus, processor, subsystem and IP blocks, enabling it to be used with different interconnect standards, future processor IP and a broad range of IP blocks. Additionally, CoreConsole delivers all relevant IP software drivers to be used with the microprocessor software program development tools.

The CoreConsole tool's Windows(TM) user interface is graphical, intuitive and easy to use, supporting the instantiation and configuration of the processor subsystem functions, Actel DirectCores, Actel CompanionCores and user-defined IP blocks. After the IP is stitched to the bus, the tool generates a system interconnect test bench that can be used to validate and debug the connection of the design within the FPGA fabric.

SPIRIT Compliant

CoreConsole uses methods defined by the Structure for Packaging, Integrating and Re-using IP within Tool-flows (SPIRIT) initiative and includes underlying structures based on XML code, allowing designers to use their SPIRIT-compliant cores and ensuring the easy transfer of IP between vendors.

Pricing and Availability

The CoreConsole IDP tool is priced at $395 for a one-year license and is available from Actel. For more information about CoreConsole, visit Actel's Web site, http://www.actel.com/products/ip/ARM7.html .

About Actel

Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit http://www.actel.com . Telephone: 888-99-ACTEL (992-2835).

NOTE: The Actel name and logo are registered trademarks of Actel Corporation. ARM7 is a trademark of ARM Limited. All other trademarks and service marks are the property of their respective owners.

CONTACT: Clive Jones of Actel Corporation, +1-650-318-4523, or
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Web site: http://www.actel.com/